1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device and method for fabricating the same for increasing aperture ratio.
2. Discussion of the Related Art
Generally, a liquid crystal display device controls light transmittance of liquid crystal using an electric field to thereby display a picture. Such a liquid crystal display device drives liquid crystal using an electric field. Herein, the electric field is provided between a pixel electrode and a common electrode opposing each other on an upper and lower substrate of a liquid crystal display device.
The liquid crystal display device may include a thin film transistor array substrate (a lower plate) and a color filter array substrate (an upper plate) opposite each other, liquid crystal between the two substrates, and a spacer for cell gap between two substrates.
The thin film transistor array substrate may be comprised of a plurality of signal lines, a thin film transistor, and an alignment film coated thereon for aligning liquid crystal. The color filter array substrate may be comprised of a color filter for implementing color, a black matrix for preventing light leakage, and an alignment film coated thereon for aligning liquid crystal.
In such a liquid crystal display, the thin film transistor array substrate may have a complex fabrication process leading to an increase in manufacturing cost of the liquid crystal display panel because it involves a semiconductor process and a plurality of mask processes. To solve this, the thin film transistor array substrate has been manufactured with a reduced number of mask processes. One mask process may include a lot of processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, etc. Recently, a four-round mask process has been developed excluding one mask process from the existent five-round mask process that was a standard mask process of the thin film transistor array substrate.
FIG. 1 is a plan view showing a portion of a thin film transistor array substrate using a related art four-round mask process, and FIG. 2 is a sectional view of the thin film transistor array substrate taken along I-I′, II-II′ in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor array substrate includes a gate line 2 and a data line 4 provided on a lower substrate 25 to intersect each other with a gate insulating film 27 therebetween, a thin film transistor 6 provided at each gate and data line intersection, a pixel electrode 14 provided at a pixel area, and a storage capacitor (not shown) provided at an overlapped portion between the gate line 2 and the pixel electrode 14.
The gate line 2 and the data line 4 substantially cross each other to define a pixel area. Herein, the gate line 2 is supplied with a gate signal, and the data line 4 is supplied with a data signal.
The thin film transistor 6 allows a pixel signal applied to the data line 4 to be charged into the pixel electrode 14 and kept in response to a gate signal applied to the gate line 2. The thin film transistor 6 may include a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 14. Also, the thin film transistor 6 may further include an active layer 21 overlapping with the gate electrode 8 with a gate insulating film 27 therebetween to define a channel portion 11 between the source electrode 10 and the drain electrode 12. On the active layer 21, an ohmic contact layer 23 for making ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further provided.
The pixel electrode 14 is connected, via a contact hole 13 passing through a protective film 29, to the drain electrode 12 of the thin film transistor 6.
Accordingly, an electric field is formed between the pixel electrode 14 supplied with a pixel signal via the thin film transistor 6 and a common electrode (not shown) supplied with a reference voltage. Liquid crystal molecules arranged between the thin film transistor array substrate and the color filter array substrate are rotated by the electric field due to dielectric anisotropy. Light transmittance of the pixel area varies depending upon a rotation extent of the liquid crystal molecules to implement a gray level scale.
The storage capacitor (not shown) allows a pixel signal charged in the pixel electrode 14 to be stably maintained until the next signal is charged.
Hereinafter, a method of fabricating the thin film transistor array substrate having the above-mentioned structure adopting the four-round mask process will be described in detail with reference to FIG. 3A to FIG. 3H.
Referring to FIG. 3A, a first conductive pattern group including the gate electrode 8 is provided on the lower substrate 25 by the first mask process.
More specifically, a gate metal layer is formed on the lower substrate 25 by a deposition technique such as sputtering, etc. Next, the gate metal layer is patterned by photolithography and an etching process using a first mask to form the first conductive pattern including the gate electrode 8. Herein, the gate metal layer may be made from an aluminum group metal, etc.
Referring to FIG. 3B, the gate insulating film 27, an amorphous silicon layer 51, a n+ amorphous silicon layer 53, and a source/drain metal layer 41 are sequentially provided on the lower substrate 25 provided with the first conductive pattern by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 27 may be formed from an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).
Next, a photo-resist 43 is formed on the source/drain metal layer 41, and then a second mask 50 is aligned at an upper portion of the lower substrate 25. The second mask 50 is comprised of a transmitting area P1 exposing ultraviolet light, a partial transmitting area P2 partially transmitting ultraviolet light, and a shielding area P3 shielding ultraviolet light. The partial transmitting area P2 of the second mask 50 may include a diffractive exposing portion or a half transmitting portion to partially transmit ultraviolet light.
The photo-resist 43 is exposed and developed by the second mask 50 to provide a photo-resist pattern 45 having step coverage at a portion corresponding to the shielding area P3 and the partial transmitting area P2 of the second mask 50 as shown in FIG. 3C. In other words, a second photo-resist pattern 45B provided at the partial transmitting area P2 has a substantially lower height than a first photo-resist pattern 45A provided at the shielding area P3.
The source/drain metal layer 41, the n+ amorphous silicon layer 53 provided at a lower portion of the source/drain metal layer 41, and the amorphous silicon layer 51 are sequentially etched and removed by the photo-resist pattern 45. A semiconductor pattern 20 is formed at the data line 4, a source-drain metal pattern 73, and a lower portion of the source-drain metal pattern 73 if the source/drain metal layer 41, the n+ amorphous silicon layer 53, and the amorphous silicon layer 51 are sequentially removed by the photo-resist pattern 45 as shown in FIG. 3D.
Next, the photo-resist pattern 45 is ashed by an ashing process using plasma gas resulting in a thinned first photo-resist pattern 45A, and is removed by the second photo-resist pattern 45B as shown in FIG. 3E. The second photo-resist pattern 45B and both sides of the first photo-resist pattern 45A are simultaneously removed by the ashing process. The source-drain metal pattern 73 and the data line 4 are removed by a wet-etching process using the first ashed photo-resist pattern 45A as shown in FIG. 3E. Herein, the source-drain metal pattern 73 and the data line 4 are exposed by the ashing process of the photo-resist pattern 45. The source-drain metal pattern 73 exposed by the ashing process is removed to provide the source electrode 10 and the drain electrode 12, and to expose the removed source-drain metal pattern 73 and the ohmic contact layer 23 under the data line 4.
The exposed ohmic contact layer 23 is removed by dry-etching using the first ashed photo-resist pattern 45A as shown in FIG. 3F, and the channel portion 11 of the thin film transistor is formed.
Next, the first photo-resist pattern 45A is removed by a stripping process as shown in FIG. 3G with reference to “d1.” The first photo-resist pattern 45A is left on the source electrode 10, the drain electrode 12, and the data line 4 (not shown).
Referring to FIG. 3B to FIG. 3G, the semiconductor pattern 20, the channel portion 11 of the thin film transistor, the source electrode 10, and the drain electrode 12 can be formed by one mask process using the photo-resist pattern 45 having step coverage. However, both sides of the data line 4, the source-drain metal pattern 43, and the ohmic contact layer 23 are again etched by the first ashed photo-resist pattern 45A. As a result, the source electrode 10, the drain electrode 12, the ohmic contact layer 23, and the active layer 21 under them 10, 12, and 23 have a constant step coverage taking a stepwise shape.
Referring to FIG. 3H, a second conductive pattern group is formed at the gate insulating film 27 by the second mask process. Herein, the second conductive pattern group includes the source electrode 10, the drain electrode 12, the channel portion 11, and the data line 4. Next, the protective film 29 including the contact hole 13 is formed on the gate insulating film 27 by a third mask process. The pixel electrode 14 is formed on the protective film 29 including the contact hole 13 by a fourth mask.
More specifically, the protective film 29 is entirely formed on the gate insulating film 27 provided with the second conductive pattern group by a deposition technique such as PECVD, etc. Next, the protective film 29 is patterned by a photolithography process and an etching process using the third mask to provide the contact hole 13. The contact hole 13 passes through the protective film 29 to expose the drain electrode 12.
A transparent conductive film is disposed on the protective film 29 by a deposition technique such as sputtering, etc. Next, the transparent conductive film is patterned by a photolithography process and an etching process using the fourth mask to provide the pixel electrode 14. The pixel electrode 14 is electrically connected, via the contact hole 13, to the drain electrode 12.
As described above, the related art thin film transistor array substrate and the fabricating method thereof adopt a four-round mask process to reduce the overall number of processes and hence reduce manufacturing cost in proportion to the reduction in the number of processes when compared to a five-round mask process.
A liquid crystal display device such as that used in a notebook, etc requires a screen brightness of approximately 500 nit (cd/m2). A liquid crystal display device manufactured by a related art five-round mask process has a screen brightness of approximately 500 nit (cd/m2) sufficient for a consumer. However, a liquid crystal display device manufactured by a four-round mask process has an aperture ratio approximately 2% lower than the liquid crystal display device manufactured by the related art five-round mask process owing to a width (d1) of step coverage formed at both sides of the data line 4 as shown in FIG. 3G and FIG. 3H. As a result, it is difficult to produce a screen brightness of approximately 500 nit (cd/m2) by the four-round mask process.
The width (d1) of step coverage formed at both sides of the data line 4 decreases aperture ratio. The reason will be described in detail with reference to FIG. 2 and FIG. 4. Herein, the data line 4 is provided by the four-round mask process and the data line 40 is provided by the five-round mask process.
FIG. 4 is a sectional view showing a data line 40 of a thin film transistor array substrate formed by a five-round mask process. The thin film transistor substrate formed by the five-round mask process results from two mask processes. Herein, one mask process forms a semiconductor pattern 30 and the other mask process forms a channel portion (not shown) of the thin film transistor, the source electrode, and the drain electrode (not shown). Since the five-round mask process does not use a mask including a partial transmitting area, a photo-resist pattern having step coverage is not formed, and an ashing process is not required. Accordingly, the data line 40 and the semiconductor pattern 30 have no step coverage, and are formed to have a width (d2) of about 3.6 μm to about 4 μm as shown in FIG. 4. Herein, the data line 40 is formed by the five-round mask process, and the semiconductor pattern 30 is formed at a lower portion thereof.
The data line 4 is formed by the four-round mask process including the second mask process as mentioned in FIG. 3B to FIG. 3G. In this case, the data line 4 is formed to have a width (d1) of about 3.6 μm to about 4 μm, and step coverage is provided between the data line 4 and the active layer 21 formed at a lower portion thereof. Herein, the step coverage has a width (d1) of about 1.7 μm at both sides of the data line 4, respectively.
FIG. 5 illustrates an actual step coverage formed between the data line provided by the four-round mask process and the active layer provided at a lower portion thereof.
The data lines 4 and 40, and the semiconductor patterns 20 and 30 disposed at a lower portion thereof are joined to correspond to the black matrix upon joining of the color filter array substrate. A non-aperture area includes a portion corresponding to the black matrix. Thus, the active layer 21 formed at a lower portion of the data line 4 by the four-round mask process has step coverage. Herein, the step coverage has a width (d1) of about 1.7 μm at both sides of the data line 4, respectively. As a result, a non-aperture area covered by the black matrix of the color filter array substrate may be wider than a non-aperture area provided by the five-round mask process. Aperture ratio is reduced as the non-aperture area becomes wide. Thus, an alternative for securing a high aperture ratio is needed.
Also, the active layer 21 formed by the four-round mask process is exposed at both sides of the data line 4. As a result, a screen waves (hereinafter, referred to as “wave noise phenomenon”).